1. Field of the Invention
The present invention relates to video processing of compressed video information, and more particularly, to a method and device for regulating the computation load of an MPEG decoder.
2. Description of Related Art
Video information is typically compressed to save storage space and decompressed in a bit stream for a display. Thus, it is highly desirable to quickly and efficiently decode compressed video information in order to provide motion video. One compression standard which has attained widespread use for compressing and decompressing video information is the Moving Pictures Expert Group (MPEG) standard for video encoding and decoding. The MPEG standard is defined in International Standard ISO/IEC 11172-1, “Information Technology—Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s”, Parts 1, 2 and 3, First edition Aug. 01, 1993 which is hereby incorporated by reference in its entirety.
In general, a goal of many video systems is to quickly and efficiently decode compressed video information so as to provide motion video. Currently, computation load of processing a frame is not constrained by the decoding algorithm in the MPEG2 decoding processor. However, due to the irregular computation load behavior of MPEG2 decoding, the peak computation load of a frame may exceed the maximum CPU load of a media processor, thereby causing frame drops or unexpected results. As a consequence, when an engineer implements MPEG2 decoding on a media processor, he or she needs to choose a processor that has a performance margin of 40%-50% above the average decoding computation load in order to have a smooth operation in the event that the peak computation load occurs. This type of implementation is uneconomical and creates a waste of resources as the undesirable peak computation load does not occur that frequently. Hence, without complexity prediction or estimation of frame, slice, or macroblock computational loads, it is impossible for video system engineers to regulate the peak computational demands of some MPEG bit streams.
Therefore, there is a need to provide complexity prediction algorithms for an MPEG2 decoder implemented on a media processor.